1. Field of the Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) power amplifier capable of being used in a wireless transmission system, and more particularly, to a CMOS power amplifier capable of improving linearity by varying a threshold voltage of an amplifying transistor according to a magnitude of an input signal to thereby reduce distortion of the signal in a linear power amplifier having a cascode structure.
2. Description of the Related Art
Generally, in accordance with the ongoing development of wireless communications, interest in the integration of a radio transceiver has gradually increased. Particularly, a complementary metal oxide semiconductor integrated chip (CMOS IC) is cheap, as compared to a compound semiconductor. Further, in the case of the CMOS IC, many auxiliary ICs may be integrated. Therefore, a large amount of research into CMOS ICs has been conducted.
Typically, since a power amplifier needs to amplify a large signal without distortion, it requires a high breakdown voltage. Therefore, a compound semiconductor such as a hetero-junction bipolar transistor (HBT), or the like, is still in use.
However, due to the development of a CMOS design together with the development of a CMOS process, interest in a CMOS power amplifier has been gradually increasing.
Recently, a power amplifier (PA), developed through the CMOS process, has been divided into a switching PA and a linear PA, according to an application thereof. In the case of an application using the switching PA, since information is only carried on a phase of the signal, linearity need not be considered.
However, in the case of an application such as wideband code division multiple access (WCDMA), or the like, information is carried on an amplitude and a phase, and thus, linearity becomes an important performance index. Therefore, significantly reducing intermodulation distortion (IMD) is required. In addition, in the case of a linear PA, since there is a trade-off relationship between linearity (IMD) and power added efficiency (PAE), IMD is required to be significantly reduced without deteriorating other characteristics.
Meanwhile, as an index showing the linearity of the linear amplifier, a value expressing magnitudes of a wanted signal among output signals and a third harmonic in decibels (dB) is used. Here, the larger a difference, the better.
As an example, the linear power amplifier according to the related art includes a single transistor, such that it may be implemented as a CMOS. In this case, since a breakdown voltage is low, the device is broken at maximum output power.
As another example, in the linear amplifier according to the related art, two transistors may be generally implemented as a cascode structure. Here, two transistors are implemented as a cascode stack, such that an operating voltage VDD is divided and used by two transistors. Therefore, a gate breakdown in power amplifiers using a single transistor according to the related art may be prevented.
In the cascode power amplifier according to the related art as described above, as a signal is input, a gate-source voltage Vgs of a transistor increases from 0. When the gate-source voltage Vgs exceeds a threshold voltage (Vth), a drain current Idrain flows.
However, in the cascode power amplifier according to the related art, in a case in which a large signal is input, when a gate-source voltage Vgs of a specific level or more is applied, the power amplifier moves into a saturation region, such that the drain current Idrain becomes constant and distortion of the signal is generated.